FIG. 1 schematically illustrates the signal voltage of PCI Express device in the prior art. Generally, the signal of PCI Express device is a kind of differential signals. A D+ signal (the solid sin wave in FIG. 1) and a D− signal (the dotted sin wave in FIG. 1) are generated by a differential voltage driver. The potential difference between the D+ signal and the D− signal is the differential voltage. When the voltage of the D+ signal is higher than the voltage of the D− signal, there is a positive potential difference which is defined as the logic “1” state. When the voltage of the D+ signal is lower than the voltage of the D− signal, there is a negative potential difference which is defined as the logic “0” state. When the potential difference reaches maximum potential difference, it can be regarded as a differential peak voltage (VDIFFp). The maximum difference between the positive potential difference and the negative potential difference is a differential peak-to-peak voltage (VDIFFp-p) which is twice of the VDIFFp. The VDIFFp-p is the signal amplitude between the logic “1” state and the logic “0” state.
Since different hosts require different signal amplitudes and the length of the transmitting line is different due to the different operating states, the transmitting amplitude of PCI Express device is prescribed to ensure that the transmitting amplitude is high enough to be received by the receiving terminal, wherein the VDIFFp-p generated by the output driver is prescribed within a range of 800 mV to 1200 mV and the VDIFFp-p which can be received by the receiving terminal is prescribed within a range of 175 mV to 1200 mV in the standard. According to the aforementioned standard, when the minimum VDIFFp-p (800 mV) is generated by the transmitting terminal, the maximum of the amplitude attenuation corresponding to the receivable VDIFFp-p of the receiving terminal is 625 mV. However, there would not be a large attenuation in most situations. Moreover, if the length of the transmitting line is ultra short, the high amplitude should be unnecessary since the data would still be received by the receiving terminal.
Various green movements are going to be carried out in the modern society. The reduction of the power consumption is one of the green movements. In PCI Express device, the high amplitude represents the large power consumption. Therefore, if the difference between the amplitude received by the receiving terminal and the minimum receivable amplitude thereof is large, the power waste is high. If the amplitude can be reduced and the stabilization of the data transmission can be maintained at the same time, the unnecessary power waste can be prevented. However, when the data amplitude is reduced, the stabilization of the data transmission can not be maintained if the minimum of the transmitting amplitudes which are large enough to be received by the receiving terminal can not be determined.
Therefore, to overcome the drawbacks from the prior art and to meet the present needs, the Applicant dedicated in considerable experimentation and research, and finally accomplished the “Method and Device of Power Saving for Transmitting Signals” of the present invention. Before the data signal is transmitted in PCI Express device, the first Training Sequence (TS1) which should be transmitted for determining whether the connection is completed is used for determining the minimum amplitude during the data signal transmitting to reduce the voltage to solve the problem that the power waste in prior art is too much. The present invention is briefly described as follows.